Elizabeth Susan Wolf (Research Page)



Synchronous Trace Theory

I have completed my thesis on synchronous trace theory:

Hierarchical Models of Synchronous Circuits for Formal Verification and Substitution

Available as Stanford technical report STAN-CS-TR-95-1557
from the Stanford Computer Science Department or
on-line via the Stanford University Electronic Library or
via this link by ftp from sprout.stanford.edu.

Synchronous trace theory provides a trace-theoretical (behavioral) model of combinational and sequential, synchronous circuitry which supports formal hierarchical verification and replacement. Some of the most interesting problems we encountered in developing this theory appear in modeling purely combinational hardware. A summary of the relevant problems and our solution appears in the second publication listed below. My thesis incorporates both the combinational and the sequential theories.


Other formal verification projects

In 1991, I participated in a formal verification project at Hewlett-Packard. The results of that project are documented in the first publication below. A more detailed version of that publication, from which fewer proprietary hardware details were deleted, appeared in the Hewlett-Packard internal Design Technology Conference in 1992, where it won Best Paper award in the "Simulation and Modeling" session.


Publications


Liz' Home Page


Elizabeth Wolf, eswolf@cs.stanford.edu
Computer Science Department, Stanford University
Last modified: November 4, 1996