Welcome to Jacob Chang's homepage

Research

I am currently at Stanford University working on verification of hardware design using formal methods. I am currently with the Formal Verification Group and verifying designs being developed for the Smart Memory project. Our current approach is to use formal methods verify the design in a top down manner as the design is being developed. This allow us to give influences to the design which will make the verification process easier. This is in contrast with methods of testing and verification after the design is done or verifying high level protocol without direct link to the actual physical design.

Publications

• Jacob Chang, Sergey Berezin, and David L. Dill. Using Interface Refinement to Integrate Formal Verification into the Design Cycle. In Proceedings of CAV'04, July 2004
  [Abs] [Bib] [PS] [PDF] [PDF Slides]
• J. Chang, S.Ravi, A. Raghunathan FLEXBAR: A crossbar switching fabric with improved performance and utilization In Proceedings CICC'02, May 2002
  [Abs] [PS] [PDF]

Contact Info

353 Serra Mall, Gates 352 Stanford, CA 94305-9030
Phone: (650)725-1683
E-mail:

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