Instructions for generating the monitor.
The Main Idea
There are five Verilog files for the monitor.
The idea is to download the four sub-module files, then go to the
monitor generating page, generate the monitor with the appropriate parameters
and download that file, and then finally, compile together all five modules
with a Verilog simulator/compiler.
Step-by-step instructions
- Download the Verilog file
counter.v
- Download the Verilog file
history.v
- Download the Verilog file
bus.v
- Download the Verilog file
buswire.v
- Download the Verilog file
main.v
- With these five files, you can now compile them using a Verilog
compiler/simulator such as VERILOG-XL. The command should be "verilog main.v
history.v counter.v bus.v buswire.v".
Usage
You can use this monitor as part of your simulation environment or simply
look at the the Verilog files to get a better feel of what we mean by a
"collection of small properties"
or a "monitor". All the Verilog files
should be readable and fairly well commented.
There are multiple uses and applications for this this PCI protocol monitor
Verilog file. It can be used as,
- A formal specification of the PCI protocol. A non-ambiguous
specification which engineers can refer to to obtain clarification. Because the
monitor is written as a collection of rules, it is an excellent form of a
specification document.
- A monitor to aid formal verification and testing of a single PCI
implementation. The monitor can be used directly to generate an environment
for the implementation being tested. There is no need to create an
implementation of the environment!
- A monitor to aid simulation testing for two or more interacting PCI
implementations. The monitor will detect cases where any implementation
breaks a protocol rule.
kannas@stanford.edu
Last modified : October 24, 2002