The conflict is between these two statements:

"TRDY# should use the address cycle as a turnaround cycle (3.2.4)"
-> TRDY# should not be driven (asserted or deasserted) during the address phase

but...

"The agent that drives an s/t/s pin low must drive it high for at least one clock before letting it float. (2.1)
-> During the address phase after a back-to-back transaction, TRDY# should be driven (high). In this scenario, TRDY# is always asserted in the cycle before the address phase, and deasserted during the address phase.